When logic gates are connected together to produce the specific output for certain specific combination of input variable with no storage involved the resulting circuit is called combinational logic circuit.
ADDERS
|
0 |
0 |
0 |
|
0 |
1 |
1 |
|
1 |
0 |
1 |
|
1 |
1 |
1 |
The higher significant bit of these result is called carry and the lower significant bit called sum.
The logic circuit which performs this operation is called a half-adder.
The operation which performs addition of three bits is a full-adder.
HALF ADDER
The half-adder operation needs two binary inputs.
|
INPUT |
OUTPUT |
|
A B |
CARRY SUM |
|
0 0 |
0 0 |
|
0 1 |
0 1 |
|
1 0 |
1 0 |
|
1 1 |
1 1 |
Limitation of half adder:
In multidigit addition we have to add to bits along with the carry of previous digit addition.
Effectively for 3 bit addition this is not possible for half adder.
FULL ADDER:
It consist of 3 input and 2 output.
|
INPUT |
OUTPUT |
|
A B C |
Carry Sum |
|
0 0 0 |
0 0 |
|
0 0 1 |
0 1 |
|
0 1 0 |
0 1 |
|
0 1 1 |
1 0 |
|
1 0 0 |
0 1 |
|
1 0 1 |
1 0 |
|
1 1 0 |
1 0 |
|
1 1 1 |
1 1 |
SUBRACTORS:
|
0- |
0= |
0 |
|
0- |
1= |
1 |
|
1- |
0= |
1 |
|
1- |
1= |
0 |
HALF SUBRACTOR:
TRUTH TABLE:
|
INPUTS |
OUTPUT |
|
A B |
Difference Borrow |
|
0 0 |
0 0 |
|
0 1 |
1 1 |
|
1 0 |
1 0 |
|
1 1 |
0 0 |
Limitations:
In multidigit subtraction, subtract 2 bits along with the previous bit.
Effectively for 3 bit subtractionthis is not possible for half subtractor.
FULL SUBTRACTOR:
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