Transistor Transistor Logic (TTL):
TTL Circuit Diagram:
2-Input TTL NAND Gates:
|
A |
B |
Y |
|
0 |
0 |
1 |
|
0 |
1 |
1 |
|
1 |
0 |
1 |
|
1 |
1 |
0 |
3-Input TTL NAND Gates:
|
A |
B |
C |
Y |
|
0 |
0 |
0 |
1 |
|
0 |
0 |
1 |
1 |
|
0 |
1 |
0 |
1 |
|
0 |
1 |
1 |
1 |
|
1 |
0 |
0 |
1 |
|
1 |
0 |
1 |
1 |
|
1 |
1 |
0 |
1 |
|
1 |
1 |
1 |
0 |
Totem Pole output:
Open-Collector output:
|
Totem Pole |
Open-Collector |
|
Output stage consist of pull-up transistor Q3 diode resistor and pull-down transistor Q4 |
Output stage consist of only pull-up transistor |
|
External pull-up resistor is not required |
External pull-up resistor is required |
|
Output of two gate cannot be tied together |
Output of two gate can be tied together with AND technique |
|
Operating speed is high |
Operating speed is low |
Tri-State TTL inverter:
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